//****************************************************************
// File Name  : AR8035_top.v
// Author     : xianyong.chen
// Date       : 
// Description: 
//   It's the top of AR8035 configuration
//****************************************************************
`timescale 1ns/1ns

module AR8035_top(
        input   wire            sclk,
        input   wire            rst_n,

        output  wire            mdc,
        inout   tri             mdio
        );
//****************************************************************
wire    [4:0]   phy_addr;
wire    [4:0]   reg_addr;
wire            wr_en;
wire    [15:0]  wr_data;
wire            wr_end;
wire            rd_en;
wire            rd_data_vld;
wire    [15:0]  rd_data;
reg             clk_enable;
//****************************************************************

always @(posedge sclk or negedge rst_n)
    if (!rst_n)
        clk_enable <= 1'b0;
    else
        clk_enable <= ~clk_enable;

//----------------------------------------
// instance of AR8035_cfg
//----------------------------------------
AR8035_cfg AR8035_cfg_inst(
        .sclk                   (sclk                   ),
        .clk_enable             (clk_enable             ),
        .rst_n                  (rst_n                  ),
                                                        
        .phy_addr               (phy_addr               ),
        .reg_addr               (reg_addr               ),
        .wr_en                  (wr_en                  ),
        .wr_data                (wr_data                ),
        .wr_end                 (wr_end                 ),
        .rd_en                  (rd_en                  ),
        .rd_data_vld            (rd_data_vld            ),
        .rd_data                (rd_data                )
        );

//----------------------------------------
// instance of AR8035_mii_phy
//----------------------------------------
AR8035_mii_phy AR8035_mii_phy_inst(
        .sclk                   (sclk                   ),
        .clk_enable             (clk_enable             ),
        .rst_n                  (rst_n                  ),
                                                        
        .phy_addr               (phy_addr               ),
        .reg_addr               (reg_addr               ),
        .wr_en                  (wr_en                  ),
        .wr_data                (wr_data                ),
        .wr_end                 (wr_end                 ),
        .rd_en                  (rd_en                  ),
        .rd_data_vld            (rd_data_vld            ),
        .rd_data                (rd_data                ),
                                                        
        .mdc                    (mdc                    ),
        .mdio                   (mdio                   )
        );
//****************************************************************
endmodule
